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1 for more information www.analog.com document feedback typical application features description low i q boost/sepic/ inverting converter with 2a, 100v switch the lt ? 8361 is a current mode dc/dc converter with a 100v, 2 a switch operating from a 2.8v to 60v input. with a unique single feedback pin architecture it is capable of boost, sepic or inverting configurations. burst mode operation consumes as low as 9a quiescent current to maintain high efficiency at very low output currents , while keeping typical output ripple below 15mv. an external compensation pin allows optimization of loop bandwidth over a wide range of input and output voltages and programmable switching frequencies between 300khz and 2mhz. a sync/mode pin allows synchronization to an external clock. it can also be used to select between burst or pulse-skip modes of operation with or without spread spectrum frequency modulation for low emi. for increased efficiency, a bias pin can accept a second input to supply the intv cc regulator. additional features include frequency foldback and programmable soft-start to control inductor current during startup. the LT8361 is available in a thermally enhanced 16-lead msop package with four pins removed for high voltage pin spacings. 400khz, 24v output sepic converter applications n wide input voltage range: 2.8v to 60v n ultralow quiescent current and low ripple burst?mode ? operation: i q = 9a n 2a, 100v power switch n positive or negative output voltage programming with a single feedback pin n programmable frequency (300khz to 2mhz) n synchronizable to an external clock n spread spectrum frequency modulation for low emi n bias pin for higher effciency n programmable undervoltage lockout (uvlo) n thermally enhanced 16-lead msop packages n industrial and automotive n telecom n medical diagnostic equipment n portable electronics all registered trademarks and trademarks are the property of their respective owners. efficiency and power loss lt 8361 rev 0 121k 10f 22h 22h 1f en/uvlo rt v in sw 1f fbx bias intv cc ss gnd v c LT8361 sync/mode 4.7f v in v out 4v to 48v 24v d1: diodes inc. dfls2100 l1: wurth elektronik we-dd 7345 744877220 c5: murata grm32er71h106ka12l 200ma at v in = 5v 450ma at v in = 12v 550ma at v in = 24v 600ma at v in = 48v efficiency power loss 6.8nf v in = 12v v in = 48v load current (a) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.22f 0.7 0 10 20 30 40 50 60 70 80 1m 90 100 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 71.5k 2.00 2.25 2.50 efficiency (%) power loss (w) 8361 ta01b 8361 ta01a 16.2k
2 for more information www.analog.com sw .......................................................................... 100 v v in , en / uvlo ........................................................... 60 v b ias .......................................................................... 60 v en / u vlo pin above v in pin, sync .............................6v intvcc ............................................................. ( no te 2) vc ............................................................................... 4 v fbx ........................................................................... 4 v o perating junction temperature ( note 3) lt 8 361 e , lt 8361 i .............................. C 40 c to 125 c lt 8 361 h ............................................ C 40 c to 150 c storage temperature range .................. C 65 c to 150 c order information lead free finish tape and reel part marking* package description temperature range LT8361emse#pbf LT8361emse#trpbf 8361 16-lead plastic msop with 4 pins removed C40c to 125c LT8361imse#pbf LT8361imse#trpbf 8361 16-lead plastic msop with 4 pins removed C40c to 125c LT8361hmse#pbf LT8361hmse#trpbf 8361 16-lead plastic msop with 4 pins removed C40c to 150c consult adi marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container. consult adi marketing for information on nonstandard lead based finish parts. for more information on lead free part marking , go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 0 r r 0 r pin configuration absolute maximum ratings (note 1) http://www .linear.com/product/LT8361#orderinfo lt 8361 rev 0
3 for more information www.analog.com parameter conditions min typ max units v in operating voltage range l 2.8 60 v v in quiescent current at shutdown v en/uvlo = 0.2v l 1 1 2 15 a a v en/uvlo = 1.5v l 2 2 5 25 a a v in quiescent current sleep mode (not switching) sync = 0v l 9 9 15 30 a a active mode (not switching) sync = 0v or int v cc , bias = 0v l 1200 1200 1600 1850 a a sync = 0v or int v cc , bias = 5v l 22 22 40 65 a a bias threshold rising, bias can supply int v cc falling, bias cannot supply intv cc 4.4 4 4.65 4.25 v v v in falling threshold to supply intv cc bias = 12v bias C 2v v bias falling threshold to supply intv cc v in = 12v v in v fbx regulation fbx regulation voltage fbx > 0v fbx < 0v l l 1.568 C0.820 1.6 C0.80 1.632 C0.780 v v fbx line regulation fbx > 0v, 2.8v < v in < 60v fbx < 0v, 2.8v < v in < 60v 0.005 0.005 0.015 0.015 %/v %/v fbx pin current fbx = 1.6v, C0.8v l C10 10 na oscillator switching frequency (f osc ) r t = 165k r t = 45.3k r t = 20k l l l 273 0.92 1.85 300 1 2 327 1.08 2.15 khz mhz mhz ssfm maximum frequency deviation (? f/f osc ) ? 100, r t = 20k 14 20 25 % minimum on-time burst mode, v in = 24v (note 6) pulse-skip mode, v in = 24v (note 6) 70 70 95 90 ns ns minimum off-time l 55 75 ns sync/mode, mode thresholds (note 5) high (rising), v in = 24v low (falling), v in = 24v l l 0.14 1.3 0.2 1.7 v v sync /mode, clock thresholds (note 5) rising, v in = 24v falling, v in = 24v l l 0.4 1.3 0.8 1.7 v v f sync /f osc allowed ratio r t = 20k 0.95 1 1.25 khz/khz sync pin current sync = 2v sync = 0v, current out of pin 10 10 25 25 a a switch maximum switch current limit threshold l 2 2.5 3.4 a switch overcurrent threshold discharges ss pin 3.75 a switch r ds(on) i sw = 0.5a 375 m switch leakage current v sw = 100v 0.1 1 a electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, en/uvlo = 12v unless otherwise noted. lt 8361 rev 0
4 for more information www.analog.com electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, en/uvlo = 12v unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: intv cc cannot be externally driven. no additional components or loading is allowed on this pin. note 3: the LT8361e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LT8361i is guaranteed over the full C40c to 125c operating junction temperature range. the LT8361h is guaranteed over the full C40c to 150c operating junction temperature range. note 4: the ic includes overtemperature protection that is intended to protect the device during overload conditions. junction temperature will exceed 150c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature will reduce lifetime. note 5: for sync/mode inputs required to select modes of operation see the pin functions and applications information sections. note 6: the ic is tested in a boost converter configuration with the output voltage programmed for 24v. parameter conditions min typ max units en/uvlo logic en/uvlo pin threshold (rising) start switching l 1.576 1.68 1.90 v en/uvlo pin threshold (falling) stop switching l 1.545 1.6 1.645 v en/uvlo pin current v en/uvlo = 1.6v l C50 50 na soft-start soft-start charge current ss = 0.5v 2 a soft-start pull-down resistance fault condition, ss = 0.1v 220 error amplifier error amplifier transconductance fbx = 1.6v fbx = C0.8v 75 60 a/v a/v error amplifier voltage gain fbx = 1.6v fbx = C0.8v 185 145 v/v v/v error amplifier max source current v c = 1.1v, current out of pin 7 a error amplifier max sink current v c = 1.1v 7 a lt 8361 rev 0
5 for more information www.analog.com typical performance characteristics switching frequency vs temperature switching frequency vs v in normalized switching frequency vs fbx voltage fbx positive regulation voltage vs temperature fbx negative regulation voltage vs temperature en/uvlo pin thresholds vs temperature switch current limit vs duty cycle switch minimum on-time vs temperature switch minimum off-time vs temperature lt 8361 rev 0 125 0 5 10 15 20 25 30 35 40 45 150 50 55 60 1.90 1.92 1.94 1.96 1.98 2.00 2.02 175 2.04 2.06 2.08 2.10 switching frequency (mhz) 8361 g05 voltage (v) ?0.8 ?0.4 0.0 1.568 0.4 0.8 1.2 1.6 0 25 50 75 100 125 1.576 normalized switching frequency (%) 8361 g06 v in = 12v duty cycle (%) 0 10 20 30 40 50 1.584 60 70 80 90 100 2.0 2.1 2.2 2.3 2.4 1.592 2.5 2.6 2.7 2.8 2.9 3.0 switch current limit (a) 8361 g07 v in = 12v v in = 12v 1.600 ?50 ?25 0 25 50 junction temperature (c) 75 100 125 150 1.608 175 0 10 20 30 40 50 60 70 80 1.616 90 100 minimum on time (ns) 8361 g08 v in = 12v ?50 ?25 0 25 50 junction temperature (c) 1.624 75 100 125 150 175 0 10 20 30 40 1.632 50 60 70 80 90 100 minimum off time (ns) 8361 g09 junction temperature (c) fbx voltage (v) 8361 g01 v in = 12v junction temperature (c) ?50 ?25 0 25 ?50 50 75 100 125 150 175 ?0.820 ?0.815 ?0.810 ?0.805 ?25 ?0.800 ?0.795 ?0.790 ?0.785 ?0.780 fbx voltage (v) 8361 g02 v in = 12v en/uvlo rising (turn?on) en/uvlo falling (turn?off) 0 junction temperature (c) ?50 ?25 0 25 50 75 100 125 150 25 175 1.54 1.56 1.58 1.60 1.62 1.64 1.66 1.68 1.70 50 1.72 1.74 en/uvlo pin voltage (v) 8361 g03 junction temperature (c) ?50 ?25 0 25 50 75 75 100 125 150 175 1.90 1.92 1.94 1.96 1.98 100 2.00 2.02 2.04 2.06 2.08 2.10 switching frequency (mhz) 8361 g04 v in = 12v v in (v)
6 for more information www.analog.com typical performance characteristics switching waveforms (in ccm) switching waveforms (in dcm/light burst mode) switching waveforms (in deep burst mode) burst frequency vs load current v out transient response: load current transients from 390ma to 790ma to 390ma v out transient response: load current transients from 150ma to 790ma to 150ma v in pin current (sleep mode, not switching) vs temperature v in pin current (active mode, not switching, bias = 0v) vs temperature v in pin current (active mode, not switching, bias = 5v) vs temperature lt 8361 rev 0 25 8361 g14 1s/div i l1 + i l2 200ma/div v sw 20v/div 8361 g15 front page application v in = 24v v out = 24v 50 100s/div v out 500mv/div i out 500ma/div 8361 g18 front page application v in = 24v v out = 24v 100s/div 75 v out 1v/div i out 500ma/div 8361 g17 front page application v in = 12v v out = 48v load current (ma) 0 100 20 40 60 80 100 0 0.5 1.0 1.5 2.0 125 2.5 switching frequency (mhz) 8361 g16 150 175 0 2 4 v in = 12 v 6 8 10 12 14 16 18 20 22 24 v bias = 0v 26 28 30 v in pin current (a) 8361 g10 v in = 12v v bias = 0v v sync_mode = float junction temperature (c) ?50 v sync_mode = 0v ?25 0 25 50 75 100 125 150 175 0 junction temperature (c) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 ?75 v in pin current (ma) 8361 g11 v in = 12v v bias = 5v v sync_mode = float junction temperature (c) ?50 ?25 0 25 ?50 50 75 100 125 150 175 10 14 18 22 ?25 26 30 34 38 42 46 50 v in pin current (a) 8361 g12 500ns/div 0 i l1 + i l2 500ma/div v sw 20v/div 8361 g13 500ns/div i l1 + i l2 200ma/div v sw 20v/div
7 for more information www.analog.com pin functions en/uvlo: shutdown and undervoltage detect pin . the LT8361 is shut down when this pin is low and active when this pin is high. below an accurate 1.6v threshold, the part enters undervoltage lockout and stops switching . this allows an undervoltage lockout (uvlo) threshold to be programmed for system input voltage by resistively dividing down system input voltage to the en/uvlo pin. an 80 mv pin hysteresis ensures part switching resumes when the pin exceeds 1.68v. en/uvlo pin voltage below 0.2v reduces v in current below 1a. if shutdown and uvlo features are not required, the pin can be tied directly to system input. v in : input supply. this pin must be locally bypassed. be sure to place the positive terminal of the input capacitor as close as possible to the v in pin , and the negative terminal as close as possible to the exposed pad pgnd copper (near en/uvlo). intv cc : regulated 3.2v supply for internal loads. the intv cc pin must be bypassed with a 1f low esr ceramic capacitor to gnd. no additional components or loading is allowed on this pin. intv cc draws power from the bias pin if 4.4v bias v in , otherwise intv cc is powered by the v in pin. nc: no internal connection. leave this pin open. bias: second input supply for powering intv cc . removes the majority of intv cc current from the v in pin to improve efficiency when 4.4v bias v in . if unused, tie the pin to gnd. v c : error amplifier output pin. tie external compensation network to this pin. fbx: voltage regulation feedback pin for positive or nega - tive outputs. connect this pin to a resistor divider between the output and the exposed pad gnd copper ( near fbx). fbx reduces the switching frequency during start-up and fault conditions when fbx is close to 0v. rt : a resistor from this pin to the exposed pad gnd cop - per (near fbx) programs switching frequency. ss: soft-start pin. connect a capacitor from this pin to gnd copper ( near fbx ) to control the ramp rate of inductor current during converter start-up. ss pin charging current is 2a. an internal 220 mosfet discharges this pin during shutdown or fault conditions. sync/mode: this pin allows five selectable modes for optimization of performance. sync/mode pin input capable mode(s) of operation (1) gnd or <0.14v burst (2) external clock pulse-skip/sync (3) 100k resistor to gnd burst/ssfm (4) float (pin open) pulse-skip (5) intv cc or >1.7v pulse-skip/ssfm where the selectable modes of operation are, burst = low i q , low output ripple operation at light loads pulse-skip = skipped pulse (s ) at light load (aligned to clock ) sync = switching frequency synchronized to external clock s sfm = spread spectrum frequency modulation for low emi sw1, sw 2 (sw): output of the internal power switch. minimize the metal trace area connected to these pins to reduce emi. pgnd,gnd: power ground and signal ground for the ic. the package has an exposed pad underneath the ic which is the best path for heat out of the package. the pin should be soldered to a continuous copper ground plane under the device to reduce die temperature and increase the power capability of the LT8361. connect power ground components to the exposed pad copper exiting near the en/ uvlo and sw pins. connect signal ground components to the exposed pad copper exiting near the v c and fbx pins. lt 8361 rev 0
8 for more information www.analog.com block diagram 8361 bd ? + ? + a7 ? + ? + a6 ? + ? + ? + a2 ? + r4 opt v bias (+) v bias ? 2v(?) 4.4v(+) 4.0v(?) 3.2v regulator sw1 sw oscillator a6 error amp select frequency foldback intv cc uvlo switch logic burst detect slope driver m1 intv cc t j > 170c 1.68v(+) 1.6v(?) internal reference uvlo c in sw2 bias r3 opt v in c out c vcc d l v out uvlo rt sync/mode over- current a7 overcurrent ? + a1 pgnd/gnd error amp error amp slope 1.6v fbx v out r2 r1 ?0.8v max i limit 1.5 max i limit r sense pwm comparator q1 r5 a3 a5 i ss 2a m2 ss c ss r c v c c c en/uvlo v in uvlo a4 lt 8361 rev 0
9 for more information www.analog.com operation the LT8361 uses a fixed frequency, current mode control scheme to provide excellent line and load regulation . operation can be best understood by referring to the block diagram. an oscillator ( with frequency programmed by a resistor at the rt pin ) turns on the internal power switch at the beginning of each clock cycle. current in the inductor then increases until the current comparator trips and turns off the power switch . the peak inductor current at which the switch turns off is controlled by the voltage on the v c pin. the error amplifier servos the v c pin by comparing the voltage on the fbx pin with an internal reference voltage (1.60v or C0.80 v, depending on the chosen topology). when the load current increases it causes a reduction in the fbx pin voltage relative to the internal reference. this causes the error amplifier to increase the v c pin voltage until the new load current is satisfied. in this manner, the error amplifier sets the correct peak switch current level to keep the output in regulation. the LT8361 is capable of generating either a positive or negative output voltage with a single fbx pin. it can be configured as a boost or sepic converter to generate a positive output voltage, or as an inverting converter to generate a negative output voltage. when configured as a boost converter, as shown in the block diagram, the fbx pin is pulled up to the internal bias voltage of 1.60v by a voltage divider (r1 and r2) connected from v out to gnd. amplifier a2 becomes inactive and amplifier a1 performs (inverting) amplification from fbx to v c . when the LT8361 is in an inverting configuration, the fbx pin is pulled down to C0.80v by a voltage divider from v out to gnd. amplifier a1 becomes inactive and amplifier a2 performs (non-inverting) amplification from fbx to v c . if the en/uvlo pin voltage is below 1.6v, the LT8361 enters undervoltage lockout (uvlo), and stops switching. when the en/uvlo pin voltage is above 1.68v (typical), the LT8361 resumes switching . if the en / uvlo pin voltage is below 0.2v, the LT8361 draws less than 1a from v in . for the sync/mode pin tied to ground or <0.14v, the LT8361 will enter low output ripple burst mode opera - tion for ultra low quiescent current during light loads to maintain high efficiency. for a 100k resistor from sync/ mode pin to gnd, the LT8361 uses burst mode opera - tion for improved efficiency at light loads but seamlessly transitions to spread-spectrum modulation of switching frequency for low emi at heavy loads . for the sync/ mode pin floating ( left open), the LT8361 uses pulse- skipping mode, at the expense of hundreds of microamps, to maintain output voltage regulation at light loads by skipping switch pulses. for the sync/mode pin tied to intv cc or >1.7v, the LT8361 uses pulse-skipping mode and performs spread-spectrum modulation of switching frequency. for the sync/mode pin driven by an external clock, the converter switching frequency is synchronized to that clock and pulse-skipping mode is also enabled. see the pin functions section for sync/mode pin. the LT8361 includes a bias pin to improve efficiency across all loads. the LT8361 intelligently chooses between the v in and bias pins to supply the intv cc for best ef- ficiency. the intv cc supply current can be drawn from the bias pin instead of the v in pin for 4.4v bias v in . protection features ensure the immediate disable of switching and reset of the ss pin for any of the following faults: internal reference uvlo, intv cc uvlo, switch cur - rent > 1.5 maximum limit, en /uvlo < 1.6v or junction temperature > 170 c. lt 8361 rev 0
10 for more information www.analog.com applications information figure 1. burst frequency vs load current achieving ultralow quiescent current to enhance efficiency at light loads the LT8361 uses a low ripple burst mode architecture . this keeps the output capacitor charged to the desired output voltage while minimizing the input quiescent current and output ripple. in burst mode operation, the LT8361 delivers single small pulses of current to the output capacitor followed by sleep periods where the output power is supplied by the output capacitor. while in sleep mode, the LT8361 consumes only 9a. as the output load decreases, the frequency of single cur - rent pulses decreases ( see figure 1) and the percentage of time the LT8361 is in sleep mode increases, resulting in much higher light load efficiency than for typical convert - ers. to optimize the quiescent current performance at light loads , the current in the feedback resistor divider must be minimized as it appears to the output as load current. in ad - dition, all possible leakage currents from the output should also be minimized as they all add to the equivalent output load. the largest contributor to leakage current can be due to the reverse biased leakage of the schottky diode ( see diode selection in the applications information section). while in burst mode operation , the current limit of the switch is approximately 400ma resulting in the output voltage ripple shown in figure 2. increasing the output capacitance will decrease the output ripple proportionally . as the output load ramps upward from zero the switching frequency will increase but only up to the fixed frequency defined by the resistor at the rt pin as shown in figure ?1. figure 2. burst mode operation the output load at which the LT8361 reaches the fixed frequency varies based on input voltage, output voltage, and inductor choice. programming input turn-on and turn-off thresholds with en/uvlo pin the en/uvlo pin voltage controls whether the LT8361 is enabled or is in a shutdown state. a 1.6v reference and a comparator a6 with built-in hysteresis ( typical 80mv ) allow the user to accurately program the system input voltage at which the ic turns on and off (see the block diagram). the typical input falling and rising threshold voltages can be calculated by the following equations: v in(falling,uvlo(?)) = 1.60 ? r3 + r4 r4 v in(rising, uvlo(+)) = 1.68 ? r3 + r4 r4 v in current is reduced below 1a when the en/uvlo pin voltage is less than 0.2v. the en/uvlo pin can be con - nected directly to the input supply v in for always-enabled operation. a logic input can also control the en/uvlo pin. when operating in burst mode operation for light load currents, the current through the r3 and r4 network can easily be greater than the supply current consumed by the LT8361. therefore, r3 and r4 should be large enough to minimize their effect on efficiency at light loads. lt 8361 rev 0 80 100 0 0.5 1.0 1.5 2.0 2.5 switching frequency (mhz) 8361 f01 front page application 10s/div i l 200ma/div v out 2mv/div 8361 f02 v in = 12v v out = 48v load current (ma) 0 20 40 60
11 for more information www.analog.com applications information intv cc regulator a low dropout (ldo) linear regulator, supplied from v in , produces a 3.2 v supply at the intv cc pin. a minimum 1f low esr ceramic capacitor must be used to bypass the intv cc pin to ground to supply the high transient cur - rents required by the internal power mosfet gate driver. no additional components or loading is allowed on this pin. the intv cc rising threshold (to allow soft-start and switching) is typically 2.65v. the intv cc falling threshold (to stop switching and reset soft-start) is typically 2.5v. to improve efficiency across all loads , the majority of intv cc current can be drawn from the bias pin (4.4v bias v in ) instead of the v in pin. for sepic applications with v in often greater than v out , the bias pin can be di - rectly connected to v out . if the bias pin is connected to a supply other than v out , be sure to bypass the pin with a local ceramic capacitor. programming switching frequency the LT8361 uses a constant frequency pwm architecture that can be programmed to switch from 300khz to 2mhz by using a resistor tied from the rt pin to ground . a table showing the necessary r t value for a desired switching frequency is in table 1. the r t resistor required for a desired switching frequency can be calculated using: r t = 51.2 f osc ? 5.6 where r t is in k and f osc is the desired switching fre - quency in mhz. table 1. sw frequency vs r t value f osc (mhz) r t (k) 0.3 165 0.45 107 0.75 63.4 1 45.3 1.5 28.7 2 20 synchronization and mode selection to select low ripple burst mode operation , for high effi- ciency at light loads, tie the sync/mode pin below 0.14v ( this can be ground or a logic low output). t o synchronize the LT8361 oscillator to an external fre - quency connect a square wave ( with 20% to 80% duty cycle) to the sync pin. the square wave amplitude should have valleys that are below 0.4v and peaks above 1.7v (up to 6v). the LT8361 will not enter burst mode operation at low output loads while synchronized to an external clock, but instead will pulse skip to maintain regulation. the LT8361 may be synchronized over a 300khz to 2mhz range. the r t resistor should be chosen to set the LT8361 switching frequency equal to or below the lowest synchronization input. for example, if the synchronization signal will be 500khz and higher, the r t should be selected for 500khz. for some applications it is desirable for the LT8361 to operate in pulse-skipping mode , offering two major differ - ences from burst mode operation. firstly, the clock stays awake at all times and all switching cycles are aligned to the clock. secondly, the full switching frequency is main - tained at lower output load than in burst mode operation. these two differences come at the expense of increased quiescent current. to enable pulse-skipping mode , float the sync pin. to improve emi /emc, the LT8361 can provide spread spectrum frequency modulation ( ssfm). this feature varies the clock with a triangle frequency modulation of 20%. for example, if the LT8361's frequency was programmed to switch at 2mhz, spread spectrum mode will modulate the oscillator between 2mhz and 2.4mhz. the 20% modula - tion will occur at a frequency: f osc /256 where f osc is the switching frequency programmed using the rt pin. the LT8361 can also be configured to operate in pulse- skipping/ssfm mode by tying the sync/mode pin above 1.7v. the LT8361 can also be configured for burst mode operation at light loads (for improved efficiency) and ssfm at heavy loads (for low emi) by tying a 100k from the sync/mode pin to gnd. lt 8361 rev 0
12 for more information www.analog.com duty cycle consideration the LT8361 minimum on-time, minimum off-time and switching frequency (f osc ) define the allowable minimum and maximum duty cycles of the converter (see minimum on-time, minimum off-time , and switching frequency in the electrical characteristics table). minimum allowable duty cycle = minimum on-time (max) ? f osc(max) maximum allowable duty cycle = 1 ? minimum off-time (max) ? f osc(max) the required switch duty cycle range for a boost converter operating in continuous conduction mode (ccm) can be calculated as: d min = 1 ? v in(max) v out + v d d max = 1 ? v in(min) v out + v d where v d is the diode forward voltage drop. if the above duty cycle calculations for a given application violate the minimum and/ or maximum allowed duty cycles for the LT8361, operation in discontinuous conduction mode?( dcm) might provide a solution. for the same v in and v out levels, operation in dcm does not demand as low a duty cycle as in ccm. dcm also allows higher duty cycle operation than ccm. the additional advantage of dcm is the removal of the limitations to inductor value and duty cycle required to avoid sub-harmonic oscillations and the right half plane zero (rhpz). while dcm provides these benefits, the trade-off is higher inductor peak cur - rent, lower available output power and reduced efficiency. set ting the output vol tage the output voltage is programmed with a resistor divider from the output to the fbx pin. choose the resistor values for a positive output voltage according to: r1 = r2 ? v out 1.60v ? 1 ? ? ? ? ? ? choose the resistor values for a negative output voltage according to: r1 = r2 ? |v out | 0.80v ? 1 ? ? ? ? ? ? the locations of r1 and r2 are shown in the block dia - gram. 1% resistors are recommended to maintain output voltage accuracy. higher-value fbx divider resistors result in the lowest input quiescent current and highest light-load efficiency. fbx divider resistors r 1 and r2 are usually in the range from 25k to 1m. soft-start the LT8361 contains several features to limit peak switch currents and output voltage (v out ) overshoot during start-up or recovery from a fault condition . the primary purpose of these features is to prevent damage to external components or the load. high peak switch currents during start-up may occur in switching regulators. since v out is far from its final value, the feedback loop is saturated and the regulator tries to charge the output capacitor as quickly as possible, resulting in large peak currents. a large surge current may cause inductor saturation or power switch failure. the LT8361 addresses this mechanism with a program - mable soft-start function . as shown in the block diagram, th e soft-start function controls the ramp of the power switch current by controlling the ramp of v c through q1. this allows the output capacitor to be charged gradually toward its final value while limiting the start-up peak currents. figure 3 shows the output voltage and supply current for the first page t ypical application. it can be seen that both the output voltage and supply current come up gradually. fault protection an inductor overcurrent fault (> 3.75a) and/ or intv cc undervoltage (intv cc < 2.5v) and/or thermal lockout (t j ? >? 170c) will immediately prevent switching , will reset the ss ? pin and will pull down v c . once all faults are removed, the LT8361 will soft-start v c and hence inductor peak current. applications information lt 8361 rev 0
13 for more information www.analog.com figure 3. soft-start waveforms applications information frequency foldback during start-up or fault conditions in which v out is very low , extremely small duty cycles may be required to maintain control of inductor peak current . the minimum on-time limitation of the power switch might prevent these low duty cycles from being achievable. in this scenario inductor current rise will exceed inductor current fall during each cycle, causing inductor current to walk up beyond the switch current limit. the LT8361 provides protection from this by folding back switching frequency whenever fbx or ss pins are close to gnd (low v out levels or start-up). this frequency foldback provides a larger switch-off time, allowing inductor current to fall enough each cycle (see normalized switching frequency vs fbx voltage in the typical performance characteristics section). thermal lockout if the LT8361 die temperature reaches 170c (typical), the part will stop switching and go into thermal lockout. when the die temperature has dropped by 5c (nominal), the part will resume switching with a soft-started inductor peak current. compensation loop compensation determines the stability and transient performance. the LT8361 uses current mode control to regulate the output which simplifies loop compensation . the optimum values depend on the converter topology , the component values and the operating conditions (including the input voltage, load current, etc.). to compensate the feedback loop of the LT8361, a series resistor-capacitor network is usually connected from the v c pin to gnd. the block diagram shows the typical v c compensation network. for most applications, the capacitor should be in the range of 100pf to 10nf, and the resistor should be in the range of 5k to 100k. a small capacitor is often connected in parallel with the rc compensation network to attenuate the v c voltage ripple induced from the output voltage ripple through the internal error amplifier. the paral - lel capacitor usually ranges in value from 2.2pf to 22pf. a p r actical approach to designing the compensation network is to start with one of the circuits in this data sheet that is similar to your application, and tune the compensation network to optimize the performance . stability should then be checked across all operating conditions, including load current, input voltage and temperature. application note 76 is a good reference. thermal considerations care should be taken in the layout of the pcb to ensure good heat sinking of the LT8361. both packages have an exposed pad underneath the ic which is the best path for heat out of the package. the exposed pad should be soldered to a continuous copper ground plane under the device to reduce die temperature and increase the power capability of the LT8361. the ground plane should be connected to large copper layers to spread heat dissipated by the LT8361. power dissipation within the LT8361 (p diss_LT8361 ) can be estimated by subtracting the inductor and schottky diode power losses from the total power losses calculated in an efficiency measurement. the junction temperature of LT8361 can then be estimated by: t j (LT8361) = t a + ja ? p diss_LT8361 application circuits the LT8361 can be configured for different topologies . the first topology to be analyzed will be the boost converter, followed by the sepic and inverting converters. boost converter: switch duty cycle the LT8361 can be configured as a boost converter for the applications where the converter output voltage is higher than the input voltage. remember that boost converters are lt 8361 rev 0 200s/div i l1 + i l2 1a/div v out 10v/div 8361 f02
14 for more information www.analog.com applications information not short-circuit protected . under a shorted output condi- tion, the inductor current is limited only by the input supply capability . for applications requiring a step-up converter that is short-circuit protected , please refer to the applica - tions information section covering sepic converters. the conversion ratio as a function of duty cycle is: v out v in = 1 1 ? d in continuous conduction mode (ccm). for a boost converter operating in ccm, the duty cycle of the main switch can be calculated based on the output voltage (v out ) and the input voltage (v in ). the maximum duty cycle (d max ) occurs when the converter has the minimum input voltage: d max = v out ? v in(min) v out discontinuous conduction mode (dcm) provides higher conversion ratios at a given frequency at the cost of re - duced efficiencies, higher switching currents, and lower available output power . boost converter: maximum output current capability and inductor selection for the boost topology , the maximum average inductor current is: i l(max)(avg) = i o(max) ? 1 1 ? d max ? 1 where (< 1.0) is the converter efficiency. due to the current limit of its internal power switch, the LT8361 should be used in a boost converter whose maxi - mum output current (i o(max) ) is: i o(max) v in(min) v out ? 2a ? 0.5 ? i sw ( ) ? minimum possible inductor value and switching frequency should also be considered since they will increase inductor ripple current ?i sw . the inductor ripple current ?i sw has a direct effect on the choice of the inductor value and the converters maximum output current capability. choosing smaller values of ?i sw increases output current capability, but requires large inductances and reduces the current loop gain (the converter will approach voltage mode ). accepting larger values of ?i sw provides fast transient response and allows the use of low inductances , but results in higher input current ripple and greater core losses, and reduces output current capability. it is recommended to choose a ?i sw of approximately 0.75a. given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor , the inductor value of the boost converter can be determined using the following equation: l = v in(min) i sw ? f osc ? d max the peak inductor current is the switch current limit (maximum 3.4a), and the rms inductor current is ap- proximately equal to i l(max)( avg ) . choose an inductor that can handle at least 3.4 a without saturating, and ensure that the inductor has a low dcr ( copper-wire resistance ) to minimize i 2 r power losses. note that in some applications, the current handling requirements of the inductor can be lower, such as in the sepic topology where each inductor only carries one-half of the total switch current. for better efficiency, use similar valued inductors with a larger volume. many different sizes and shapes are available from various manufacturers ( see table 2). choose a core material that has low losses at the programmed switch - ing frequency, such as a ferrite core . the final value chosen for the inductor should not allow peak inductor currents to exceed 2 a in steady state at maximum load. due to toler - ances, be sure to account for minimum possible inductance value , switching frequency and converter efficiency. for inductor current operation in ccm and duty cycles above 50%, the LT8361' s internal slope compensa - tion prevents sub-harmonic oscillations provided the inductor value exceeds a minimum value given by : l > v in ?5 ?d 2 + 9 ?d ? 1 ( ) ? f osc ( ) ? 2 ?d ? 1 ( ) 1?d ( ) lower l values are allowed if the inductor current operates in dcm or duty cycle operation is below 50%. lt 8361 rev 0
15 for more information www.analog.com table 2. inductor manufacturers sumida (847) 956-0666 www.sumida.com tdk (847) 803-6100 www.tdk.com murata (714) 852-2001 www.murata.com coilcraft (847) 639-6400 www.coilcraft.com wurth (605) 886-4385 www.we-online.com boost converter: input capacitor selection bypass the input of the LT8361 circuit with a ceramic ca - pacitor of x7r or x5r type placed as close as possible to the v in and gnd pins. y5 v types have poor performance over temperature and applied voltage, and should not be used. a 4.7f to 10f ceramic capacitor is adequate to bypass the LT8361 and will easily handle the ripple cur - rent. if the input power source has high impedance, or there is significant inductance due to long wires or cables , additional bulk capacitance may be necessar y. this can be provided with a low performance electrolytic capacitor . a precaution regarding the ceramic input capacitor con - cerns the maximum input voltage rating of the LT8361. a ceramic input capacitor combined with trace or cable inductance forms a high quality ( under damped) tank cir - cuit. if the LT8361 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the LT8361s voltage rating. this situation is easily avoided (see application note 88). boost converter: output capacitor selection low esr (equivalent series resistance) capacitors should be used at the output to minimize the output ripple voltage. multilayer ceramic capacitors are an excellent choice, as they are small and have extremely low esr. use x5r or x7r types. this choice will provide low output ripple and good transient response. a 4.7f to 47f output capacitor is sufficient for most applications , but systems with very low output currents may need only a 1f or 2.2f output capacitor. solid tantalum or os-con capacitor can be used, but they will occupy more board area than a ceramic and will have a higher esr. always use a capacitor with a sufficient voltage rating. contributions of esr (equivalent series resistance), esl (equivalent series inductance) and the bulk capacitance must be considered when choosing the correct output capacitors for a given output ripple voltage. the effect of these three parameters ( esr, esl and bulk c) on the output voltage ripple waveform for a typical boost converter is illustrated in figure 4. the choice of component(s) begins with the maximum acceptable ripple voltage ( expressed as a percentage of the output voltage), and how this ripple should be divided between the esr step ?v esr and the charging /discharg- ing ? v cout . for the purpose of simplicity, we will choose 2% for the maximum output ripple, to be divided equally between ?v esr and ?v cout . this percentage ripple will change, depending on the requirements of the application, and the following equations can easily be modified . for a 1% contribution to the total ripple voltage, the esr of the output capacitor can be determined using the following equation: esr cout 0.01 ? v out i d(peak) for the bulk c component, which also contributes 1% to the total ripple: c out i o(max) 0.01 ? v out ? f osc the output capacitor in a boost regulator experiences high rms ripple currents, as shown in figure 4. the rms ripple current rating of the output capacitor can be determined using the following equation: i rms(cout) i o(max) ? d max 1 ? d max figure 4. the output ripple waveform of a boost converter v out (ac) t on v esr ringing due to total inductance (board + cap) v cout 8361 f04 t off applications information lt 8361 rev 0
16 for more information www.analog.com multiple capacitors are often paralleled to meet esr requirements. typically, once the esr requirement is satisfied, the capacitance is adequate for filtering and has the required rms current rating. additional ceramic capaci - tors in parallel are commonly used to reduce the effect of parasitic inductance in the output capacitor , which reduces high frequency switching noise on the converter output. ceramic capacitors ceramic capacitors are small , robust and have very low esr. however, ceramic capacitors can cause problems when used with the LT8361 due to their piezoelectric nature. when in burst mode operation, the LT8361s switching frequency depends on the load current, and at very light loads the LT8361 can excite the ceramic capacitor at audio frequencies, generating audible noise. since the LT8361 operates at a lower current limit during burst mode op - eration, the noise is typically very quiet to a casual ear. if this is unacceptable, use a high performance tantalum or electrolytic capacitor at the output. low noise ceramic capacitors are also available. applications information figure 5. suggested boost converter layout table 3. ceramic capacitor manufacturers taiyo yuden (408) 573-4150 www.t-yuden.com avx (803) 448-9411 www.avxcorp.com murata (714) 852-2001 www.murata.com boost converter: diode selection a schottky diode is recommended for use with the LT8361. low leakage schottky diodes are necessary when low quiescent current is desired at low loads . the diode leakage appears as an equivalent load at the output and should be minimized. choose schottky diodes with sufficient reverse voltage ratings for the target applications. table 4. recommended schottky diodes part number average forward current (a) reverse voltage (v) reverse current ( a) manufacturer dfls1100 1 100 1 diodes, inc. b1100/b 1 100 500 diodes, inc. dfls2100 2 100 1 diodes, inc. 1 3 5 6 7 8 en v in intv cc nc bias v c 16 14 12 11 10 9 sw1 sw2 sync ss rt fbx pgnd gnd v out sw v out pgnd v in sw 8361 f05 lt 8361 rev 0
17 for more information www.analog.com applications information boost converter: layout hints the high speed operation of the LT8361 demands careful attention to board layout. careless layout will result in per - formance degradation. figure 5 shows the recommended component placement for a boost converter . note the vias under the exposed pad. these should connect to a local ground plane for better thermal performance. sepic converter applications the LT8361 can be configured as a sepic (single-ended primary inductance converter ), as shown in figure 6. this topology allows for the input to be higher , equal, or lower than the desired output voltage . the conversion ratio as a function of duty cycle is: v out + v d v in = d 1 ? d in continuous conduction mode (ccm). figure 6. LT8361 configured in a sepic topology the maximum duty cycle (d max ) occurs when the converter operates at the minimum input voltage: d max = v out + v d v in(min) + v out + v d conversely, the minimum duty cycle (d min ) occurs when the converter operates at the maximum input voltage: d min = v out + v d v in(max) + v out + v d be sure to check that d max and d min obey: d max < 1 ? minimum off-time (max) ? f osc(max) and d min > minimum on-time (max) ? f osc(max) where minimum off-time , minimum on-time and f osc are specified in the electrical characteristics table. sepic converter: the maximum output current capability and inductor selection as shown in figure 6, the sepic converter contains two inductors: l 1 and l2. l 1 and l2 can be independent, but can also be wound on the same core , since identical voltages are applied to l1 and l2 throughout the switching cycle. for the sepic topology, the current through l1 is the converter input current. based on the fact that, ideally, the output power is equal to the input power, the maximum average inductor currents of l1 and l2 are: i l1(max)(avg) = i in(max)(avg) = i o(max) ? d max 1 ? d max i l2(max)(avg) = i o(max) in a sepic converter, the switch current is equal to i l1 + i l2 when the power switch is on, therefore, the maximum average switch current is defined as: i sw(max)(avg) = i l1(max)(avg) + i l2(max)(avg) = i o(max) ? 1 1 ? d max in a sepic converter , no dc path exists between the input and output . this is an advantage over the boost converter for applications requiring the output to be disconnected from the input source when the cir cuit is in shutdown. sepic converter: switch duty cycle and frequency for a sepic converter operating in ccm, the duty cycle of the main switch can be calculated based on the output voltage (v out ), the input voltage (v in ) and the diode forward voltage (v d ). lt 8361 rev 0 LT8361 v in v cc int d1 c in c out c dc 8361 f06 l1 l2 v out v in sw fbx gnd en/uvlo
18 for more information www.analog.com applications information and the peak switch current is: i sw(peak) = 1 + 2 ? ? ? ? ? ? ? i o(max) ? 1 1 ? d max the variable c in the preceding equations represents the percentage peak-to-peak ripple current in the switch , relative to i sw(max)( avg ) , as shown in figure 7. then, the switch ripple current ?i sw can be calculated by: ? i sw = ? i sw(max)(avg) the inductor ripple currents ?i l1 and ?i l2 are identical: ? i l1 = ? i l2 = 0.5 ? ? i sw given an operating input voltage range, and having cho - sen ripple current in the inductor, the inductor value (l1 and l 2 are independent) of the sepic converter can be determined using the following equation: l1 = l2 = v in(min) 0.5 ? i sw ? f osc ? d max for most sepic applications, the equal inductor values will fall in the range of 2.2h to 100h. by making l 1 = l 2, and winding them on the same core, the value of inductance in the preceding equation is replaced by 2l, due to mutual inductance: l = v in(min) i sw ? f osc ? d max this maintains the same ripple current and energy storage in the inductors. the peak inductor currents are: i l1(peak) = i l1(max) + 0.5 ? ? i l1 i l2(peak) = i l2(max) + 0.5 ? ? i l2 the maximum rms inductor currents are approximately equal to the maximum average inductor currents. based on the preceding equations, the user should choose the inductors having sufficient saturation and rms cur - rent ratings. similar to boost converters , the sepic converter also needs slope compensation to prevent subharmonic oscillations while operating in ccm . the equation presented in the boost converter section defines the minimum inductance value to avoid sub-harmonic oscillations when coupled inductors are used. for uncoupled inductors, the minimum inductance requirement is doubled. sepic converter: output diode selection to maximize efficiency , a fast switching diode with a low forward drop and low reverse leakage is desirable . the average forward current in normal operation is equal to the output current. 8361 f07 i sw = ? i sw(max)(avg) i sw t dt s i sw(max)(avg) t s figure 7. the switch current waveform of the sepic converter the inductor ripple current has a direct effect on the choice of the inductor value. choosing smaller values of ?i l requires large inductances and reduces the current loop gain (the converter will approach voltage mode). accepting larger values of ?i l allows the use of low in - ductances, but results in higher input current ripple and greater core losses . it is recommended that c falls in the range of 0.5 to 0.8. due to the current limit of its internal power switch, the LT8361 should be used in a sepic converter whose maximum output current (i o(max) ) is: i o(max) < (1 ? d max ) ? (2a ? 0.5 ? ? i sw ) ? where (< 1.0) is the converter efficiency. minimum possible inductor value and switching frequency should also be considered since they will increase inductor ripple current ?i sw . lt 8361 rev 0
19 for more information www.analog.com it is recommended that the peak repetitive reverse voltage rating v rrm is higher than v out + v in(max) by a safety margin (a 10v safety margin is usually sufficient). the power dissipated by the diode is: p d = i o(max) ? v d where v d is diode s forward voltage drop, and the diode junction temperature is: t j = t a + p d ? r ja the r ja used in this equation normally includes the r jc for the device, plus the thermal resistance from the board, to the ambient temperature in the enclosure. t j must not exceed the diode maximum junction temperature rating. sepic converter: output and input capacitor selection the selections of the output and input capacitors of the sepic converter are similar to those of the boost converter . sepic converter: selecting the dc coupling capacitor the dc voltage rating of the dc coupling capacitor (c dc , as shown in figure 6) should be larger than the maximum input voltage: v cdc > v in(max) c dc has nearly a rectangular current waveform. during the switch off-time, the current through c dc is i in , while approxi- mately Ci o flows during the on-time. the rms rating of the coupling capacitor is determined by the following equation: i rms(cdc) > i o(max) ? v out + v d v in(min) a low esr and esl, x5r or x7r ceramic capacitor works well for c dc . inverting converter applications the LT8361 can be configured as a dual-inductor inverting topology, as shown in figure 8. the v out to v in ratio is: v out ? v d v in = ? d 1 ? d in continuous conduction mode (ccm). inverting converter : switch duty cycle and frequency for an inverting converter operating in ccm , the duty cycle of the main switch can be calculated based on the negative output voltage (v out ) and the input voltage (v in ). the maximum duty cycle (d max ) occurs when the converter has the minimum input voltage: d max = v out ? v d v out ? v d ? v in(min) conversely, the minimum duty cycle (d min ) occurs when the converter operates at the maximum input voltage : d min = v out ? v d v out ? v d ? v in(max) be sure to check that d max and d min obey : d max < 1 ? minimum off-time (max) ? f osc(max) and d min > minimum on-time (max) ? f osc(max) where minimum off-time , minimum on-time and f osc are specified in the electrical characteristics table. inverting converter: inductor, output diode and input capacitor selections the selections of the inductor, output diode and input capacitor of an inverting converter are similar to those of the sepic converter. please refer to the corresponding sepic converter sections. applications information figure 8. a simplified inverting converter c dc v in c in l1 d1 c out v out 8361 f10 + gnd LT8361 sw l2 + ? + ? + lt 8361 rev 0
20 for more information www.analog.com applications information inverting converter: output capacitor selection the inverting converter requires much smaller output capacitors than those of the boost, flyback and sepic converters for similar output ripples . this is due to the fact that, in the inverting converter, the inductor l2 is in series with the output, and the ripple current flowing through the output capacitors are continuous. the output ripple voltage is produced by the ripple current of l2 flowing through the esr and bulk capacitance of the output capacitor: v out(p?p) = i l2 ? esr cout + 1 8 ? f osc ? c out ? ? ? ? ? ? ? ? after specifying the maximum output ripple, the user can select the output capacitors according to the preceding equation . the esr can be minimized by using high quality x 5r or x7r dielectric ceramic capacitors. in many applications, ceramic capacitors are sufficient to limit the output volt - age ripple. the rms ripple current rating of the output capacitor needs to be greater than: i rms(cout) > 0.3 ? ? i l2 inverting converter: selecting the dc coupling capacitor the dc voltage rating of the dc coupling capacitor (c dc , as shown in figure 8) should be larger than the maximum input voltage minus the output voltage (negative voltage): v cdc > v in(max) + v out c dc has nearly a rectangular current waveform. during the switch off-time, the current through c dc is i in , while approximately Ci o flows during the on-time. the rms rating of the coupling capacitor is determined by the fol- lowing equation: i rms(cdc) > i o(max) ? d max 1 ? d max a low esr and esl, x5r or x7r ceramic capacitor works well for c dc . lt 8361 rev 0
21 for more information www.analog.com typical applications 400khz, 4v to 60v input, 24v sepic converter efficiency 450khz, 3v to 60v input, 12v sepic converter efficiency lt 8361 rev 0 r1 8361 ta03a v in = 5v v in = 12v v in = 24v v in = 48v load current (a) 0.001 0.01 0.1 1 1m 50 55 60 65 70 75 80 85 90 95 r2 100 efficiency (%) 8361 ta02b v in = 5v v in = 12v v in = 24v v in = 48v load current (a) 0 0.2 71.5k 0.4 0.6 0.8 1.0 1.2 50 55 60 65 70 r3 75 80 85 90 95 100 efficiency (%) 8361 ta03b 16.2k r4 121k d1 c5 c4 10f l1 22h l2 22h c6 1f en/uvlo rt v in 1f sw fbx bias intv cc ss gnd v c LT8361 sync/mode v in c1 v out 4v to 48v 24v d1: diodes inc. dfls2100 l1: wurth elektronik we-dd 7345 744877220 c5: murata grm32er71h106ka12l 200ma at v in = 5v 450ma at v in = 12v 550ma at v in = 24v 600ma at v in = 48v v out 8361 ta02a 4.7f c4 1f c1 4.7f c3 4.7nf c2 10nf r1 1m c3 r2 154k r3 28k r4 107k d1 c5 10f l1 6.8nf 22h l2 22h c6 1f en/uvlo rt v in sw fbx c2 bias intv cc ss gnd v c LT8361 sync/mode v in v out 3v to 60v 0.22f 12v d1: diodes inc. b1100lb l1: wurth elektronik we-dd 1280 744873220 c5: murata grm32er71h106ka12l 150ma at v in = 3v 390ma at v in = 5v 700ma at v in = 12v 900ma at v in = 24v 970ma at v in = 36v 1.1a at v in = 48v 2 v out
22 for more information www.analog.com typical applications 450khz, 10v to 48v input, 48v sepic converter 2mhz, 10v to 54v input, 65v boost converter efficiency efficiency lt 8361 rev 0 r1 0 0.15 0.30 0.45 0.60 0.75 50 55 60 65 1m 70 75 80 85 90 95 100 efficiency (%) 8361 ta04b v in = 12v r2 v in = 24v v in = 48v load current (a) 0 0.1 0.2 0.3 0.4 0.5 0.6 34.8k 0 10 20 30 40 50 60 70 80 90 r3 100 efficiency (%) 8361 ta05b 24k r4 107k d1 c5 c4 10f l1 47h l2 47h c6 1f en/uvlo rt v in 1f sw fbx bias intv cc ss gnd v c LT8361 sync/mode v in c1 v out 10v to 48v 48v d1: diodes inc. dfls2100 l1: wurth elektronik we-dd 1280 744873470 c5: murata grm32er71h106ka12l 250ma at v in = 10v 290ma at v in = 12v 460ma at v in = 24v 550ma at v in = 36v 610ma at v in = 48v v out 4.7f 8361 ta04a c4 1f c1 4.7f c3 2.2nf c2 10nf r1 c3 1m r2 25.5k r3 22.1k r4 20k d1 c5 1.5f 3.3nf l1 6.1h en/uvlo rt v in sw fbx bias intv cc ss c2 gnd v c LT8361 sync/mode v in v out 10v to 54v 65v d1: diodes inc. dfls2100 l1: wurth elektronik we-pd 1280 74477006 c5: nippon chemi-con kts101b155m43n0t00 120ma at v in = 12v 10nf 310ma at v in = 24v 470ma at v in = 36v 560ma at v in = 48v 630ma at v in = 54v 2 8361 ta05a v in = 12v v in = 24v v in = 48v load current (a)
23 for more information www.analog.com typical applications 450khz, 5v to 60v input, 80v boost converter efficiency 1.2mhz, 8v to 16v input, 25v to 80v output boost converter efficiency lt 8361 rev 0 r1 0.10 0.20 0.30 0.40 0.50 0 10 20 30 40 1m 50 60 70 80 90 100 efficiency (%) 8361 ta06b v in = 12v, v out = 80v v in = 12v, v out = 25v r2 load current (a) 0 0.10 0.20 0.30 0.40 0.50 0 10 20 20.5k 30 40 50 60 70 80 90 100 efficiency (%) 8361 ta07b r3 30k r4 107k d1 c5 c4 3.3f l1 68h en/uvlo rt v in sw fbx bias intv cc 1f ss gnd v c LT8361 sync/mode v in v out 5v to 60v 80v d1: diodes inc. dfls2100 l1: wurth elektronik we-pd 1280 744770168 c5: nippon chemi-con kts101b335m55n0t00 c1 220ma at v in = 12v 450ma at v in = 24v 500ma at v in = 48v 2 8361 ta06a c4 1f c1 4.7f c3 4.7f 2.2nf c2 10nf r1 1m r2 30.4k r3 22.1k r4 c3 37.4k d1 c5 1.5f l1 6.1h r5 60k en/uvlo rt 3.3nf v in sw fbx bias intv cc ss gnd v c LT8361 sync/mode c2 v in v out 8v to 16v 25v to 80v v c ontrol 0v to 3.3v v out 80v to 25v d1: diodes inc. dfls2100 l1: wurth elektronik we-pd 1280 74477006 c5: nippon chemi-con kts101b155m43n0t00 25v/480ma at v in = 12v 10nf 48v/230ma at v in = 12v 60v/180ma at v in = 12v 80v/100ma at v in = 12v 3 8361 ta07a v in = 5v v in = 12v v in = 24v load current (a) 0
24 for more information www.analog.com typical applications 450khz, 4v to 60v input, C24v inverting converter 450khz, 3v to 60v input, C12v inverting converter efficiency efficiency lt 8361 rev 0 r1 v in = 5v v in = 12v v in = 24v v in = 48v load current (a) 0 0.2 0.4 0.6 0.8 1m 0.9 50 55 60 65 70 75 80 85 90 r2 95 100 efficiency (%) 8361 ta08b v in = 5v v in = 12v v in = 24v v in = 48v load current (a) 0 34.8k 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 r3 50 55 60 65 70 75 80 85 90 95 36.5k 100 efficiency (%) 8361 ta09b r4 107k d1 c5 c4 10f l1 33h l2 33h c6 1f en/uvlo rt v in 1f sw fbx bias intv cc ss gnd v c LT8361 sync/mode v in c1 v out 4v to 60v ?24v d1: diodes inc. dfls2100 l1: wurth elektronik we-pd 1280 744873330 c5: murata grm32er71h106ka12l 150ma at v in = 5v 500ma at v in = 12v 750ma at v in = 24v 870ma at v in = 36v 920ma at v in = 48v 8361 ta08a 4.7f c4 1f c1 4.7f c3 1.5nf c2 10nf r1 1m c3 r2 71.5k r3 59k r4 107k d1 c5 10f l1 2.2nf 22h l2 22h c6 1f en/uvlo rt v in sw fbx c2 bias intv cc ss gnd v c LT8361 sync/mode v in v out 3v to 60v 10nf ?12v d1: diodes inc. dfls2100 l1: wurth elektronik we-pd 1280 744873220 c5: murata grm32er71h106ka12l 150ma at v in = 3v 380ma at v in = 5v 680ma at v in = 12v 860ma at v in = 24v 920ma at v in = 36v 2 1a at v in = 48v 8361 ta09a
25 for more information www.analog.com typical applications 450khz, 10v to 48v input, C48v inverting converter efficiency lt 8361 rev 0 r1 1m r2 16.9k r3 48.7k r4 107k d1 c5 c4 10f l1 47h l2 47h c6 1f en/uvlo rt v in 1f sw fbx bias intv cc ss gnd v c LT8361 sync/mode v in c1 v out 10v to 48v ?48v d1: diodes inc. b1100lb l1: wurth elektronik we-pd 1280 744873470 c5: murata grm32er71h106ka12l 250ma at v in = 10v 290ma at v in = 12v 470ma at v in = 24v 550ma at v in = 36v 610ma at v in = 48v 8361 ta10a 4.7f v in = 12v v in = 24v v in = 48v load current (a) 0 0.1 0.3 0.4 0.5 0.7 c3 50 55 60 65 70 75 80 85 90 95 2.2nf 100 efficiency (%) 8361 ta10b c2 10nf
26 for more information www.analog.com typical applications conducted emi performance (cispr25 class 5 peak) conducted emi performance (cispr25 class 5 average) radiated emi performance (cispr25 class 5 peak) radiated emi performance (cispr25 class 5 average) low i q , low emi, 400khz, 24v output sepic converter with ssfm lt 8361 rev 0 c8 70 80 peak conducted emi (dbv) 8361 ta11b 12v input to 24v output at 500ma, f sw = 400khz, ssfm on class 5 average limit measured emissions ambient noise frequency (mhz) 0.1 4.7f 1 10 30 ?40 ?30 ?20 ?10 0 10 20 c10 30 40 50 60 average conducted emi (dbv) 8361 ta11c 12v input to 24v output at 500ma, f sw = 400khz, ssfm on class 5 peak limit measured emissions ambient noise 1f frequency (mhz) 0 100 200 300 400 500 600 700 800 c12 900 1000 ?20 ?10 0 10 20 30 40 50 6.8nf 60 peak radiated emi (dbv/m) 8361 ta11d 12v input to 24v output at 500ma, f sw = 400khz, ssfm on class 5 average limit measured emissions ambient noise frequency (mhz) 0 100 c13 200 300 400 500 600 700 800 900 1000 ?20 0.22f ?10 0 10 20 30 40 50 60 average radiated emi (dbv/m) 8361 ta11e r6 1m c3 r7 71.5k r8 16.2k r9 121k d2 c14 10f l1a 0.1f 22h l1b 22h c15 1f c2 68f 50v c1 0.1f c4 l2 0.1f r1 100k v out 24v v in 5v to 48v input emi filter output emi filter 50v c6 50v 35v 0402 35v 0402 50v 1210 en/uvlo r t v in 10f sw fbx bias intv cc ss gnd v c LT8361 sync/mode d1: diodes inc. dfls2100 l1: wurth elektronik we-dd 7345 744877220 l2: wurth elektronik 74479876147 c2: panasonic eehzc1h680p c14: murata grm32er71h106ka12l fb2: wurth elektronik 742792040 fb2 2 1206 100v 1206 35v 0402 35v 0402 470nh 1210 c7 v out 8361 ta11a 12v input to 24v output at 500ma, f sw = 400khz, ssfm on class 5 peak limit measured emissions ambient noise frequency (mhz) 0.1 1 10 0.1f 30 ?20 ?10 0 10 20 30 40 50 60
27 for more information www.analog.com information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. package description msop (mse16(12)) 0213 rev d 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 1.0 (.039) bsc 1.0 (.039) bsc 16 16 14 121110 1 3 5 6 7 8 9 9 1 8 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref mse package variation: mse16 (12) 16-lead plastic msop with 4 pins removed exposed die pad (reference ltc dwg # 05-08-1871 rev d) please refer to http://www .linear.com/product/LT8361#packaging for the most recent package drawings. lt 8361 rev 0
28 for more information www.analog.com ? analog devices, inc. 2018 d16802-0-4/18(0) www.analog.com related parts typical application part number description comments lt8300 100v in micropower isolated flyback converter with 150v/260ma switch v in = 6v to 100v, low i q monolithic no-opto flyback, 5-lead tsot - 23 lt8330 60v, 1a, low i q boost/sepic/inverting 2mhz converter v in = 3v to 40v, v out(max) = 60v, i q = 6a (burst mode operation), 6-lead tsot-23, 3mm 2mm dfn packages lt8331 low i q boost/sepic/flyback/inverting converter with 140v/0.5a switch v in = 4.5v to 100v, v out(max) =140v, i q = 6a (burst mode operation), msop-16(12)e lt8362 60v, 2a, low iq boost/sepic/inverting converter v in = 2.8v to 60v, v out(max) = 60v, i q = 9a (burst mode operation), msop-16(12)e 3mm 3mm dfn-8 packages lt8364 60v, 4a, low iq boost/sepic/inverting converter v in = 2.8v to 60v, v out(max) = 60v, i q = 9a (burst mode operation), msop-16(12)e 4mm 3mm dfn-12 packages lt8494 70v, 2a boost/sepic 1.5mhz high efficiency step-up dc/dc converter v in = 1v to 60v (2.5v to 32v start-up), v out(max) = 70v, i q = 3a (burst mode operation), i sd = <1a, 20-lead tssop lt8570/lt8570-1 65v, 500ma/250ma boost/inverting dc/dc converter v in(min) = 2.55v, v in(max) = 40v, v out(max) = 60v, i q = 1.2ma, i sd = <1ma, 3mm 3mm dfn-8, msop-8e lt8580 1a (i sw ), 65v, 1.5mhz, high efficiency step-up dc/dc converter v in : 2.55v to 40v, v out(max) = 65v, i q = 1.2ma, i sd = <1a, 3mm 3mm dfn-8, msop-8e efficiency 450khz, 4.5v to 12v input, C150v output, automotive lidar apd bias power supply lt 8361 rev 0 r1 1m r2 5.36k 8361 ta12a r3 56.2k r4 107k d1 c4 c5 1.5f l1 2.2h c6 2.2f d2 r5 20 d3 1f r6 20 d4 c7 1.5f c9 1f en/uvlo rt v in c1 sw fbx bias intv cc ss gnd v c LT8361 sync/mode v in 4.7f v out 4.5v to 12v ?150v d1, d2, d3, d4: diodes inc. dfls2100 l1: wurth elektronik we-pd 7345 7447779002 c5: nippon chemi-con kts101b155m32n0t00 v out 2 15ma v in = 5v v in = 8v v in = 12v c3 load current (ma) 0 4 8 12 16 20 0 10 20 4.7nf 30 40 50 60 70 80 90 100 efficiency (%) 8361 ta12b c2 10nf

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